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toshiba toshiba corporation 1/20 tlcs-90 series TMP90PH44 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90PH44n/TMP90PH44f 1. outline and characteristics the TMP90PH44 is a system evaluation lsi having a built-in one-time prom for (16k byte) for tmp90c844. a programming and veri?ation for the internal prom is achieved by using a general eprom programmer with an adapter socket. the function of this device is exactly the same as the tmp90c844 by programming to the internal prom. the different points between TMP90PH44 and tmp90c844 are the memory size (rom/ram). the TMP90PH44n is in a shrink dual inline package. (sdip64-p-750) the TMP90PH44f is in a quad flat package. (qfp64-p-1420a) the following are the memory map of TMP90PH44 and tmp90c844. figure 1.1. TMP90PH44 figure 1.2. tmp90c844 parts no. rom ram package adapter socket no. TMP90PH44n otp 16384 x 8bit 512 x 8bit 64-sdip bm1148 (under development) TMP90PH44f 64-qfp bm1149 (under development) www.datasheet.in
2/20 toshiba corporation TMP90PH44 figure 1. 3. TMP90PH44 block diagram www.datasheet.in
toshiba corporation 3/20 TMP90PH44 2. pin assignment and functions the TMP90PH44 pin assignment input/output pins name and functions are shown below. 2.1 pin assignment diagram the TMP90PH44n pin assignment are shown in figure 2.1 (1). figure 2.1 (1). pin assignment (shrink dip) www.datasheet.in
4/20 toshiba corporation TMP90PH44 the TMP90PH44f pin assignment are shown in figure 2.1 (2). figure 2.1 (2). pin assignment (flat package) www.datasheet.in
toshiba corporation 5/20 TMP90PH44 2.2 pin names and functions the TMP90PH44 has mcu mode and prom mode. (1) mcu mode (the tmp90c844 and the TMP90PH44 are pin compatible). table 2.2 pin names and functions (1/2) pin name no. of pins i/o or tristate function p00 ~ p07 /ad0 ~ ad7 8 i/o port 0: an 8-bit i/o port. each bit can be set for input or output. /tristate address/data bus: operates as an 8-bit bidirectional address bus or data bus when using external memory p10 ~ p17 /a8 ~ a15 8 i/o port 1: an 8-bit i/o port. each bit can be set for input or output. output address bus:operates as an address bus (upper 8 bits) when using external memory. p20 ~ p27 /sb0 ~ sb7 /w ait 8 (8) (1) i/o port 2: an 8-bit i/o port. each bit can be set for input or output. slave bus: when used a s a slave processor, operates as the slave bue for the transfer data to and from the master processor. /input wait: used as an input pin when memory or perpheral lsis with slow access times are controlled. p30 ~ p37 8 i/o port 3: 8-bit i/o port which allows i/o selection on bit basis (with programmable pull-up resistor). /swr (1) /input slave write: the strobe signal input to write data from the master processor. /srd (1) /input slave read: the strobe signal used by the master processor to read data. /scs (1) /input slave chip select: the chip select signal input from the master processor. c/d (1) input command/data: the command/data select signal input from the master processor. /st a (1) /output status output: used to report the slave bus status to the master processor. rxd (1) input serial receive data /sclk (1) /i/o serial clock /txd (1) /output serial transmit data p40 ~ p47 8 i/o port 4: 8-bit i/o port which allows i/o section on bit basis (with programmable pull-up resistor). /to1, 3, 4, 5 (4) /output timer outputs 1, 3, 4, and 5: output for timer 0, or timer 1, timer 2, timer 3 and timer 4 (2 lines). /ti0, 2, 4, 5 (4) /input timer inputs 0, 2, 4, and 5: input for timer 0, or timer 1, timer 2 and timer 4 (2 lines). /int0 (1) /input interrupt request terminal 0: interrupt request pin 0: level/rise edge programmable interrupt request pin /int1 (1) /input interrupt request terminal 1: interrupt request pin 1: rise/fall edge programmable interrupt request pin. int2 (1) /input interrupt request terminal 2: interrupt request pin 2: rise edge interrupt request pin. p50 ~ p53 /an0 ~ an3 4 input port 50 ~ 53: 1-bit output ports. analog input: 4 analog inputs to a/d converter. p56 /rd 1 output port 56: a 1-bit output port. read: strobe signal output for reading external memory. www.datasheet.in
6/20 toshiba corporation TMP90PH44 table 2.2 pin names and functions (2/2) (2) prom mode pin name no. of pins i/o or tristate function p57 /wr 1 output port 57: a 1-bit output port. write: strobe signal output for writing external memory. p60 ~ p63 /m00 ~ m03 4 i/0 /output port 6: 4-bit i/o port which allows i/o selection on bit basis. stepping motor control port 0 or pattern generation port 0. p70 ~ p73 /m10 ~ m13 4 i/o output port 7: 4-bit i/o port which allows i/o selection on bit basis. stepping motor control port 0 or pattern generation port 1. ale 1 output address latch enable clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up internally during resetting. ea 1 input external access: connects with v cc pin in the TMP90PH44 built rom is used. reset 1 input reset: initializes the TMP90PH44. (pull-up resistance is built-in). x1, x2 2 i/o crystal oscillator connection pin vref 1 input of reference voltage to a/d converter agnd 1 gnd pin for a/d converter v cc 1 power supply (+5v +/- 10%) gnd 1 gnd pin (0v) table 2.3 pin function name no. of pins i/o function pin name (mcu mode) a7 ~ a0 8 input program memory address input p73 ~ p70 p63 ~ p60 a13 ~ a8 6 input p15 ~ p10 a14 2 input be fixed to ??level , p16 a15 p17 d7 ~ d0 8 i/0 data input/output p07 ~ p00 oe 1 input output enable input p26 ce 1 input chip enable input p27 vpp 1 power supply 12.5v/5v (programming power supply) ea vcc 1 power supply 5v vcc vss 1 power supply 0v vss pin name no. of pins i/o pin setting p20 ~ p27 8 input be fixed to ??level. p40 ~ p44 5 input be fixed to ? or h?level. p45, p46 2 input be fixed to ??level. p47 1 input be fixed to ? or h?level. p50 ~ p53 p30 ~ p37 4 8 input be fixed to ? or h?level. vref 1 be fixed to ??level. agnd 1 be fixed to ??level. reset 1 input be fixed to ??level. clk 1 input be fixed to ??level. ale 1 output open x1 1 input resonator connection pin x2 1 output www.datasheet.in
toshiba corporation 7/20 TMP90PH44 3. operation the TMP90PH44 is the otp version of the tmp90c844 that is replaced an internal rom from mask rom to eprom. the function of TMP90PH44 is exactly the same as that of tmp90c844 except the internal rom/ram size. refer to the tmp90c844 except the functions which are not described this section. the following is an explanation of the hardware con?uration and operation in the relation to the TMP90PH44. the TMP90PH44 has an mcu mode and a prom mode. 3.1 mcu mode (1) mode setting and function the mcu mode is set by opening the clk pin (output status). in the mcu mode, the operation is the same as that of tmp90c844. (2) memory map figure 1.1 and figure 1.2 show the memory map of TMP90PH44 and tmp90c844. figure 3.1 shows the memory map of TMP90PH44, and the accessing area by the respective addressing mode. figure 3.1. TMP90PH44 memory map 3.2 prom mode (1) mode setting and function prom mode is set by setting the reset and clk pins to the ??level. the programming and veri?ation for the internal prom is achieved by using a general eprom programmer with the adaptor socket. the device selection (rom type) should be ?7256?with following conditions. size: 256k-bit (32k x 8-bit) vpp: 12.5v tpw: 1msec figure 3.2 shows the setting of pins in prom mode. www.datasheet.in
8/20 toshiba corporation TMP90PH44 figure 3.2. prom mode pin setting (2) programming flow chart the programming mode is set by applying 12.5v (programming v oltage) to the vpp pin when the following pins are set as follows, (vcc : 6.0v) *these conditions can be (reset ): ??level) obtained by using adaptor (clk) : ??level) socket. after the address and data have been ?ed, a data on the data bus is programmed when the ce pin is set to ?ow?(1ms plus is required). general programming procedure of an eprom programmer is as follows, ?write a data to a speci?d address for 1ms. ?verify the data. if the read-out data does not match the expected data, another writing is performed until the correct data is written (max. 25 times). after the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. then, verify the data and increment the address. the veri?ation for all data is done under the condition of vpp = vcc = 5v after all data were written. figure 3.3 shows the programming ?w chart. www.datasheet.in
toshiba corporation 9/20 TMP90PH44 figure 3.3. flow chart www.datasheet.in
10/20 toshiba corporation TMP90PH44 4. electrical characteristics (preliminary) TMP90PH44n/TMP90PH44f 4.1 absolute maximum ratings symbol parameter rating unit v cc power supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 85 c) f 500 mw n 600 t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -20 ~ 70 c (1 ~ 16mhz) typical values are for ta = 25 c and vcc = 5v. symbol parameter min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p4, p5, p6, p7 -0.3 0.3v cc v v il2 reset , p45 (into) -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3, p4, p5, p6, p7 0.7v cc v cc + 0.3 v v ih2 reset , p45 (int0) 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) (note) -1.0 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 1 35 (typ) 1.5 (typ) 50 5 ma ma tosc = 16mhz stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 40 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) 2.0 6.0 v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w c io pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , p45) 0.4 1.0 (typ) v www.datasheet.in
toshiba corporation 11/20 TMP90PH44 4.3 ac characteristics v cc = 5v 10% ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t osc oscillation cycle ( = x) 80 1000 80 62.5 ns t cyc clk period 4x 4x 320 250 ns t wh clk high width 2x - 40 120 85 ns t wl clk low width 2x - 40 120 85 ns t al a0 ~ 7 effective address ? ale fall 0.5x - 15 25 16 ns t la ale fall ? a0 ~ 7 hold 0.5x - 15 25 16 ns t ll ale pulse width x - 40 40 23 ns t lc ale fall rd /wr fall 0.5x - 30 10 1 ns t cl rd /wr ? ale rise 0.5x - 20 20 11 ns t acl a0 ~ 7 effective address ? rd /wr fall x - 25 55 38 ns t ach upper effective address ? rd /wr fall 1.5x - 50 70 44 ns t ca rd /wr fall ? upper address hold 0.5x - 20 20 11 ns t adl a0 ~ 7 effective address ? effective data input 3.0x - 35 205 153 ns t adh upper effective address ? effective data input 3.5x - 55 225 164 164 ns t rd rd fall ? effective data input 2.0x - 50 110 75 ns t rr rd pulse width 2.0x - 40 120 85 ns t hr rd rise ? data hold 0 0?ns t rae rd rise ? address enable x - 15 65 48 ns t ww wr pulse width 2.0x - 40 120 85 ns t dw effective data ? wr rise 2.0x - 50 110 75 ns t wd wr rise ? effective data hold 0.5x - 10 30 21 ns t ackh upper address ? clk fall 2.5x - 50 150 106 ns t ackl lower address ? clk fall 2.0x - 50 110 75 ns t ckha clk fall ? upper address hold 1.5x - 80 40 13 ns t cck rd /wr ? clk fall x - 25 55 37 ns t ckhc clk fall ? rd /wr rise x - 60 20 2 ns t dck valid data clk fall x - 50 30 12 ns t cwa rd /wr fall ? valid wait x - 40 40 22 ns 4.4 a/d conversion characteristics v cc = 5v 10% ta = -020 ~ 70 c f = 1 ~ 16mhz symbol parameter condition min max unit v ref analog reference voltage vcc - 1.5 vcc vcc v a gnd analog reference voltage vss vss vss v ain analog input voltage range vss vcc iref supply current for analog reference voltage 0.5 1.0 ma error (quantize error of 0.5 lsb not included) total error (ta = 25 c, vcc = v ref = 5.0v) 1.0 lsb total error 2.5 www.datasheet.in
12/20 toshiba corporation TMP90PH44 4.5 zero-cross characteristics v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 v ac p - p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.6 timer/ counter input clock (ti0, ti2, and ti4) v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t vck clock cycle 8x + 100 740 600 ns t vckl low clock pulse width 4x + 40 360 290 ns t vckh high clock pulse width 4x + 40 360 290 ns 4.7 interrupt operation v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t intal int0 low level pulse width 4x 320 250 ns t intah int0 high level pulse width 4x 320 250 ns t intbl int1, int2 low level pulse width 8x + 100 740 600 ns t intbh int1, int2 high level pulse width 8x + 100 740 600 ns 4.8 serial channel timing-i/o interface mode (1) sclk input mode v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk cycle 16x 1.28 1 m s t oss output data ? rising edge of sclk t scy /2 - 5x - 50 190 137 ns t ohs sclk rising edge ? output data hold 5x -100 300 212 ns t hsr sclk rising edge ? input data hold 0 0?ns t srd sclk rising edge ? effective data input t scy - 5x - 50 780 587 ns www.datasheet.in
toshiba corporation 13/20 TMP90PH44 (2) sclk output mode symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk cycle (programmable) 16x 8192x 1.28 655.4 1 512 m s t oss output data ? rising edge of sclk t scy - 2x - 50 970 725 ns t ohs sclk rising edge ? output data hold 2x - 80 80 45 ns t hsr sclk rising edge ? input data hold 0 0?ns t srd sclk rising edge ? effective data input t scy - 2x - 150 970 725 ns 4.9 slave bus interface timing: rd , wr bus mode v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter min max unit t sar c/d setup ? srd fall 20 ns t hra srd rise ? c /d hold 5 ns t scr scs setup ? srd fall 0 ns t hrc srd rise ? scs hold 0 ns t wrd srd pulse width 120 ns t ard srd fall ? effective data output 80 ns t vrb srd rise ? effective data hold 10 85 ns t saw c/d setup ? swr fall 20 ns t hwa swr rise ? c /d hold 5 ns t scw scr setup ? swr fall 0 ns t hwc swr rise ? scs hold 0 ns t wwr swr pulse width 120 ns t sbw effective data input ? swr rise 80 ns t hwb swr rise ? effective data hold 10 ns slave bus interface timing: ds , r/w bus mode symbol parameter min max unit t sad c/d setup ? ds fall 20 ns t hda ds rise ? c/d hold 5 ns t scd scs setup ? ds fall 0 ns t hdc ds rise ? scs hold 0 ns t sad scs setup ? ds fall 20 ns t hda ds rise ? r/w hold 5 ns t wds ds pulse width 120 ns t ads ds fall ? effective data output 80 ns t vdb ds rise ? effective data hold 10 85 ns t sbd effective data input ? ds rise 80 ns t hdb ds rise ? effective data hold 10 ns www.datasheet.in
14/20 toshiba corporation TMP90PH44 4.10 read operation (prom mode) tcyc = 400ns (10mhz clock) a = 200ns 4.11 programming operation (prom mode) st a change timing x = 1/fosc symbol parameter variable 16mhz clock unit min max min max t rph sta fall after output buffer is read 2x + 50 175 ns t wph sta rise after input buffer is written 2x + 50 175 ns dc characteristic, ac characteristic ta = -40 ~ 85 c vcc = 5v 10% symbol parameter condition min max unit v pp v ih1 v il1 v pp read voltage input high voltage (a0 ~ a15, ce , oe ) input low voltage (a0 ~ a15, ce , oe ) 4.5 0.7 x v cc -0.3 5.5 vcc + 0.3 0. 3 x v cc v v v t acc address to output delay c l = 50 p f 2.25tcyc + a ns dc characteristic, ac characteristic ta = 25 5 c vcc = 6v 0.25v symbol parameter condition min typ max unit v pp v ih v il v ih1 v il1 i cc i pp programming voltage input high voltage (d0 ~ d7) input low voltage (d0 ~ d7) input high voltage (a0 ~ a15, ce , oe ) input low voltage (a0 ~ a15, ce , oe ) v cc supply current v pp supply current f osc = 10mhz v pp = 13.00v 12.25 0.2v cc + 1.1 -0.3 0.7v cc -0.3 12.50 12.75 v cc + 0.3 0.2v cc - 0.1 v cc + 0.3 0.3v cc 50 50 v v v v v ma ma t pw ce programming pulse width c l = 50 p f 0.95 1.00 1.05 ms www.datasheet.in
toshiba corporation 15/20 TMP90PH44 4.12 timing chart www.datasheet.in
16/20 toshiba corporation TMP90PH44 4.13 timing chart for i/o interface mode www.datasheet.in
toshiba corporation 17/20 TMP90PH44 4.14 timing chart for slave bus interface: rd , wr bus mode (1) read operation (2) write operation www.datasheet.in
18/20 toshiba corporation TMP90PH44 4.15 timing chart for slave bus interface: ds , r/w bus mode (1) read operation (2) write operation www.datasheet.in
toshiba corporation 19/20 TMP90PH44 4.16 read operation timing chart (prom mode) www.datasheet.in
20/20 toshiba corporation TMP90PH44 4.17 programming operation timing chart (prom mode) www.datasheet.in

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